(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device having a layered gate electrode and, more particularly, to a method for forming an improved structure of the layered gate electrode including a polysilicon film and a metal silicide film.
(b) Description of the Related Art
MOSFETs are most important elements in a current semiconductor device having a finer and finer structure. In such a current semiconductor device, the gate electrode of the MOSFET generally has a layered structure including a polysilicon film and a metal silicide film.
FIGS. 3A to 3D are sectional views of a conventional MOSFET having a layered gate structure during consecutive steps of fabrication thereof. The MOSFET is used, for example, in a semiconductor memory device (DRAM). First, an element isolation structure and diffused regions are formed on a p-type semiconductor substrate 11 by known techniques, followed by consecutive deposition of a 7-nm-thick gate oxide film 12, a 10 nm-thick polysilicon film 13, a 120-nm-thick tungsten silicide film 14, and a 200-nm-thick silicon nitride film. Thereafter, a photoresist film is formed thereon, and patterned using a photolithographic process to form a photoresist pattern 15.
The silicon nitride film is then patterned by an anisotropic etching technique using the photoresist pattern 15 as an etching mask, thereby forming a nitride hard mask 16 to obtain the structure shown in FIG. 3A. Subsequently, the photoresist pattern 15 is removed, followed by etching the tungsten silicide film 14 and the polysilicon film 13 by using the nitride hard mask 16 as an etching mask to thereby obtain a gate electrode pattern, as shown in FIG. 3B.
Thereafter, a heat treatment is conducted at a temperature of 1000 degrees C. for 60 seconds to oxidize the side surfaces of the gate electrode pattern, thereby forming 5-nm-thick side-wall oxide films 19 thereon, as shown in FIG. 3C. The side-wall oxide film 19 alleviates the electric field at the edge of the gate electrode. Subsequently, impurity ions are implanted by using a known ion-implantation technique to form n-type diffused regions 20 on the semiconductor substrate 11. Further, a side-wall cover film 21 is formed on the gate electrode pattern by deposition and etching techniques, followed by deposition of an interlevel dielectric film 22 to embed the gate electrodes and the gap therebetween, as shown in FIG. 3D. Thereafter, other constituent elements including contact plugs and interconnects are formed by known techniques to obtain the final structure of the DRAM.
It is to be noted in the above structure of the DRAM that the side surfaces of the tungsten silicide film 14 are exposed during etching of the polysilicon film 13 as shown in FIG. 3B. Thus, the exposed surfaces of the tungsten silicide film 14 are also etched to form particles 23, which contaminate the substrate surface in the diffused regions 20 formed in the subsequent step. The contamination of the diffused regions 20 causes a problem of increase of the leakage current in the resultant MOSFET.
In addition, there arises another problem of an offset in the side-wall oxide film 19 formed on the sides of the gate electrode structure, as shown in FIG. 3C, due to the fact that the tungsten silicide film 14 is oxidized at a higher rate compared to the polysilicon film 13. The offset causes a specified location 24 to have less amount of dosage after the ion-implantation, whereby the MOSFETs have degraded transistor characteristics and may suffer from a lower product yield of non-defective MOSFETs. For avoiding the problem of offset in the side-wall oxide film, it may be considered that the amount of oxidation for the side surfaces of the gate electrode is set lower; however, this results in a degradation of refresh characteristic in the DRAM.
Moreover, the offset in the side-wall oxide film 19 raises a problem on the overall structure of the gate electrode, which may cause a void 25 in the embedding interlayer dielectric film 22. This also reduces the product yield of non-defective MOSFETs.
In view of the above, it is an object of the present invention to provide a method for manufacturing a semiconductor device, which is capable of protecting the substrate surface against the contamination by metal silicide particles and suppressing the offset of the side surfaces of the gate electrode to improve the refresh characteristic of the semiconductor device implemented as a DRAM.
The present invention provides a method for manufacturing a semiconductor device including the consecutive steps of: forming a gate oxide film, a first silicon film and a metal silicide film consecutively on a semiconductor substrate; selectively etching the metal silicide film; covering at least side surfaces of the metal silicide film by a second silicon film; selectively etching the first silicon film; and forming a gate electrode structure including the first and second silicon films and the metal silicide film.
In accordance with the method of the present invention, the second silicon film covering the side surfaces of the metal silicide film prevents metal silicide particles from dropping and scattering onto diffused regions of the semiconductor substrate during etching the first silicon film, whereby transistor characteristics of the resultant semiconductor device can be improved.
The first and second silicon films and the metal silicide film may be replaced by first through third conductive films, respectively, the first and third conductive films being made of a first conductive material, the second conductive film being made of a second conductive material.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.